1. Field of the Invention
This invention relates to a non-volatile semi-conductor memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory) in which data can be electrically rewritten.
2. Description of the Related Art
An EEPROM is formed such that a MOS transistor having a floating gate and a control gate is used as a memory cell, and a gate insulation film lying under the floating gate is made thin enough to cause a tunnel effect. When data is programmed, for example, the control gate is set to 0 V and a voltage of approx. 12 V is applied to a source or drain of the memory cell to emit electrons from the floating gate to the drain or source so as to initialize data stored in the memory cell. Then, data is selectively written into the memory cell by applying a high voltage to the control gate, setting the potential of the source to 0 V and applying a high voltage to the drain or setting the potential of the drain to 0 V. That is, if a high voltage is applied to the drain, a current flows into the memory cell and electrons generated at this time are injected into the floating gate. When the potential of the drain is kept at 0 V, no electrons are generated and the floating gate is kept in the initialized state. Thus, a binary data is stored according to the state in which electrons are injected into the floating gate or the initialized state of the floating gate. The threshold voltage of the memory cell is so set that a selected memory cell can be made conductive and a non-selected memory cell will be kept in the non-conductive state when the floating gate is kept in the initialized state. On the other hand, the threshold voltage of the memory cell is so set that the memory cell can always be set in the non-conductive state irrespective whether the memory cell is selected or not when electrons are injected into the floating gate.
FIGS. 10 and 11 show the conventional EEPROM having a plurality of memory cells which are the same as the above-described memory cell and arranged in a matrix form and FIG. 12 shows the cross section taken along the line 12--12 of FIG. 11.
As shown in FIG. 10, the memory cells M are arranged in a matrix form, the sources thereof are connected to a source line SL, the control gates of the memory cells which are arranged on the same row are connected to a corresponding one of row lines WL1 to WL4 and the drains of the memory cells which are arranged on the same column are connected to a corresponding one of column lines BL1 to BL3. With this construction, when data is initialized, electrons are first injected into the floating gates of all of the memory cells. Then, the row lines WL1 to WL4 are set to 0 V and the source line SL is set to a high voltage to emit electrons from the floating gates. If electrons of an excessive amount are emitted at the time of emission of electrons, the threshold voltage of the memory cell is set to a negative value. The memory cell having the negative threshold voltage will be made conductive even in the non-selected state. As a result, even when a memory cell which has electrons injected into the floating gate thereof and which is set in the non-conductive state is selected, a current flows out from a non-selected memory cell whose threshold voltage is negative, thereby making it impossible to correctly read out data. Therefore, when electrons are emitted from the floating gate of the memory cell, the emission state of electrons emitted from the floating gate is checked by reading out data from the memory cell after electrons are emitted for a preset period of time. If it is detected that the amount of emitted electrons is insufficient as the result of checking, electrons are emitted from the floating gate again, then data is read out, and thus, the operations of emission of electrons and data readout are repeatedly performed until the threshold voltage of the memory cell is set to an adequate value.
Thus, in the conventional EEPROM, since it is necessary to repeatedly perform the operations of emission of electrons and data readout, a control circuit for effecting the complicated control operation is required. Therefore, it becomes necessary to use a large-scale peripheral circuit, thereby increasing the chip size.
Further, the threshold voltages of the memory cells are not equal to one another and vary in a preset range after the emission of electrons from the floating gate. The threshold voltage of the memory cell is preferably set at a low level in order to enhance the data readout speed. However, since it is required to prevent the lowest threshold voltage from being set to be negative, the highest threshold voltage becomes a certain level. The degree of variation in the threshold voltage of the memory cell depends on a variation in the thickness of the gate insulation film of the memory cell and becomes different for each chip or manufacturing lot for some reasons caused in the manufacturing process. The data readout speed from the memory cell in which the degree of variation in the threshold voltage is small is high, but the data readout speed from the memory cell in which the degree of variation in the threshold voltage is large is not high. This phenomenon indicates that the difference in the data readout speed is further increased when a power supply voltage of 3 V is used as in the recent cases.
For example, a case wherein the threshold voltages of the memory cells in one chip vary between 1 V and 2 V is considered. When a power supply voltage of 5 V is used, a voltage of 5 V is applied to the control gate of a selected memory cell. Accordingly, since a current in the memory cell varies in proportion to a value obtained by subtracting the threshold voltage from the gate voltage of the memory cell when this case is briefly considered, the current varies between values corresponding to (5 V - 1 V) and (5 V - 2 V). Consequently, the ratio of the current in the memory cell in which the largest current flows to the current in the memory cell in which the smallest current flows is 4 V/3 V=1.33. However, if the power supply voltage is 3 V, the ratio of the currents becomes 2 V/1 V=2 and thus the degree of a variation in the current becomes larger. As a result, the degree of a variation in the data readout speed becomes larger.